Power consumption in electronic devices can be approximated by the equation P=VI. Power consumption is equal to the value of the DC supply voltage multiplied by the amount of consumed current from the supply. Power consumption can be decreased by lowering the voltage supply (such as from five volts to three and one third volts) and or decreasing the amount of current consumed. The decrease in DC supply voltage from five volts to three volts will approximately decrease power consumption by forty percent. With the increase of portable electronics and battery operated systems the power consumption and operation time of portable units has become important. Electronics technology has charged from TTL to CMOS in order to decrease the current consumption thereby reducing power consumption. To further decrease power consumption it is desirable that the operating voltage be reduced.
Thus, to achieve low power consumption in portable computer systems it is necessary to operate at voltages below the present 5 V CMOS and TTL DC power supply of 5.0 V (volts) plus or minus 0.5 V. JEDEC (Joint Electronic Development Engineering Committee) specified two standards for low power systems known as LVCMOS (Low Voltage CMOS or 3.3 V CMOS) and LVTTL (Low Voltage TTL). Both of these standards require circuitry to operate with a 3.3 V plus or minus 0.3 V power supply. Other low voltage standards, such as LVBO CMOS (Low Voltage Battery Operated CMOS) which operates with a DC power supply of 2.8 V plus or minus 0.8 V, are being prepared by JEDEC at this time. Each of these standards specify logic level values for inputs (VIH and VIL) and outputs (VOH and VOL). VIL is the maximum voltage at the input of the input buffer that will be recognized as logical zero. VIH is the minimum voltage level at the input of the input buffer that will be recognized as logical one. In a CMOS fabrication process output voltages generally range from ground to the maximum supply voltage. Thus for 3.3 V CMOS the typical logic levels are 0 V to represent logical zero and 3.3 V to represent logical one. In 5 V CMOS the typical logic levels are 0 V to represent logical zero and 5 V to represent logical one. However, in TTL fabrication the typical logic levels are 0.4 V to represent a logical zero and 2.4 V to represent a logical one. It is generally desirable to design a system with one type of logic family with similar logic levels. However due to the lengthy development cycle of integrated circuits, it may be a few years before note-book and hand-held computer designers have all the components necessary to design a complete system operating with only a 3.3 V DC power supply. Presently most floppy disk and hard disk controller integrated circuits that interface with the ISA or EISA bus require a 5.0 V power supply. Most flat panel and CRT Monitor display controllers require a 5.0 V power supply as well. Presently most microprocessors and DRAMs require a 5.0 V power supply to operate.
A system designer may need to design a system that operates with devices using a mixed set of DC power supplies. For example the designer may desire to design a system using a 3.3 V memory, a 5.0 V ISA bus, and internal core logic operating with a 3.3 V power supply. Hence there is a need for integrated circuit components that operate internal core logic using a 3.3 V power supply to conserve power and can simultaneously interface with other system components that generate 5 V CMOS, TTL, 3.3 V CMOS, or LVTTL logic levels from their respective DC power supplies.
In both mixed-voltage and low-voltage-only systems it is sometimes necessary to overdrive a bidirectional pin (also referred to as an Input/Output pin) with an input voltage that is greater than the DC supply voltage for the electronics of that bidirectional pin. For example assume the DC supply voltage is 3.3 V. This device may have to receive an input signal that reaches a value of 5 V from another device that has a DC supply voltage of 5 V. It is also possible that transmission line effects will cause the input voltage to ring above 3.3 V. In any case, it is desirable that power is not excessively consumed and that electronic components are not damaged.
Some prior-art methods for interfacing components of mixed DC supply voltages (also referred to as multiple DC supply voltages) to generate various logic levels use external components, such as diode clamps or voltage translators. Other prior-art methods use open-collector or open-drain output buffers that require an external pull-up resistor. These methods consume power because of extra current drawn from one of the DC supplies. Furthermore, many prior-art methods consider only unidirectional signals and not bidirectional signals, such as those within a data bus. Also such external components use space that is often very valuable, such as within a portable computer. Such additional components also reduce the reliability of a system.
This overdrive or overvoltage condition input at a pin of an integrated circuit was thought to be resolved by the PN junctions of the output transistors or the input protection diodes for an input only pin. Normally these diodes were reversed biased and had no effect on the electronic operation. However if the voltage applied to the pin becomes greater than the DC supply for that pin the diode forward biases. The diode then sinks current from the overvoltage source in order to reduce and maintain the amplitude at approximately 0.6 V above the DC supply voltage. This input protection diode current increases power consumption. In systems that use mixed DC voltage power supplies the input protection diode current can be considerable and cause damage to electronic circuits. In the case of CMOS devices excessive input protection diode current can lead to an effect called "latch-up". Thus, in low voltage (low power) CMOS systems it is desirable that a different approach to handle overvoltage conditions and mixed DC voltage power supplies be found. This would reduce power consumption and decrease the potential for circuit damage.
FIG. 1 represents the schematic of a prior-art CMOS bidirectional I/O buffer. In this case the pin of the integrated circuit has a P-type transistor pull-up 150. Thus, a separate input protection diode is not needed because the PN junction between the transistor drain and the n-well (or n substrate as the case may be) of the P-type transistor 150 is a natural diode. This diode is reverse biased for input voltage levels below the DC supply voltage VDD.
Assume that the I/O buffer of FIG. 1 is in an input mode. Assume that the DC supply voltage VDD 120 is set to 3.3 V. If the input voltage tries to overshoot or ring above VDD+0.6 V, the diode between the P-type transistor drain and substrate will sink current and increase power consumption.
Now assume VDD 120 is set to 5.0 V and the I/O buffer is in the input mode such that the output buffer is tristated. Assume that 3.3 V CMOS logic level signals are input to the PAD at node 101 where a logical one is represented by a voltage level of 3.3 V. The inverter that consists of transistors 160 and 161 has 3.3 V applied to their respective gate connections. Because VDD is set to 5 V and 3.3 V is applied to the gates of transistors 160 and 161 both transistors are in their on state. In this case each transistor is conducting and causes a current to flow from VDD to Ground (also referred to as VSS). In this document this current is referred to as a crowbar current and becomes nearly zero when either transistor 160 or 161 reach an off state. The off state for transistor 160 is reached when the input voltage at the PAD is above a value of VDD minus one P-type transistor threshold (VDD-VTP). The off state for transistor 161 is reached when the input voltage at the PAD is below a value of one N-type transistor threshold (VTN). Thus it is desirable to eliminate the crowbar current to decrease power consumption while supporting mixed logic level signals.
The prior-art tristate output buffer consists of a P-type power transistor 150, an N-type power transistor 151, a NAND gate pre-driver (consisting of transistors 152, 153, 154, 155), and a NOR gate pre-driver (consisting of transistors 156, 157, 158, and 159). Signal OEN* 103 is a signal from the core logic that tristates the power transistors 150 and 151. The "*" after a signal name represents that the signal is active low. Thus OEN* is an active low signal. In the case that the output buffer is tristated OEN* is logical one. OEN* is inverted by the inverter consisting of transistors 164 and 165 to generate OEN signal 104. If OEN* is a logical one OEN is a logical zero. OEN* is input to the NOR pre-driver at transistors 157 and 158. In this case OEN* is a logical one and forces the NOR output 111 to be a logical zero. Thus, transistor 151 is turned off because the gate voltage is 0 V. OEN 104 is input into the NAND pre-driver at transistors 154 and 152. In this case OEN is a logical zero and the NAND output 110 is forced to a logical one. Thus transistor 150 is turned off because the gate voltage is VDD volts. For the case that OEN* is a logical one, power transistors 150 and 151 are both off thereby tristating the output buffer.
In the case that the output buffer is turned on and not tristated, OEN* 103 is a logical zero. OEN 104 is a logical one. The NAND pre-driver is enabled and acts like an inverter of DO signal 102. Similarly the NOR pre-driver is enabled and acts like an inverter of DO signal 102. If DO 102 is a logical one, both the NAND pre-driver output 110 and the NOR pre-driver output 111 are logical zero. This turns on transistor 150 and keeps transistor 151 turned off. The PAD output 101 is charged towards VDD to represent a logical one. In the case that DO 102 is a logical zero, both the NAND pre-driver output 110 and the NOR pre-driver output 111 are logical one. This turns on transistor 151 and keeps transistor 150 turned off. The PAD output 101 is discharged towards Ground to represent a logical zero.
To conserve power the core logic that generates the signals OEN* 103 and DO 102 may have the power supply reduced. With the reduced power supply, the voltage representing binary logical values for OEN* and DO may be reduced to a range of 0 V to 3.3 V. The logic one value represented by 3.3 V is insufficient to properly drive an output buffer with a 5 V power supply. The 3.3 V causes crowbar currents in the output buffer. The PAD voltage levels are reduced from the normal range of 0 to 5 V. The rise, fall, and propagation times are greatly effected by the core logic voltage difference. Therefore it is desirable that the core logic with a different supply voltage be able to properly drive an output buffer.
Please note in the figures that wires crossing over do not connect unless the cross-over is highlighted by a darkened circle such as that at node 110. Wires that join at a "T" are understood to represent a connection and may also be highlighted by a darkened circle. Input protection resistor 190 is used to protect the gate oxide of transistors 160 and 161 from static charges that suddenly occur from handling a device. The resistor absorbs some of the energy that is transferred into the integrated circuit from an external source.